Poly-silicon tft, poly-silicon array substrate and preparing method thereof, display device

ABSTRACT

Provided are a poly-silicon thin film transistor (TFT), a poly-silicon array substrate and a preparing method thereof, and a display device for solving the problems of excessive mask plates, complicated process and high costs in a conventional technology. The method of preparing the poly-silicon TFT comprising a doped region comprises steps: forming a poly-silicon layer on a substrate, forming an active layer by a patterning process; forming a first insulating layer; forming, by a patterning process, via holes exposing the active layer, the source electrode and the drain electrode being connected through the via holes to the active layer; doping the active layer through the via holes by a doping process to form a doped region; forming a source-drain metal layer, and forming the source electrode and the drain electrode by a patterning process.

TECHNICAL FIELD

Embodiments of the present invention relate to a poly-silicon TFT, apoly-silicon array substrate and a preparing method thereof, and adisplay device.

BACKGROUND

With such characteristics as small volume, low power consumption andless manufacturing costs, thin film transistor liquid crystal displays(TFT-LCDs) have dominated the current market of flat panel displays.

As for the TFT using low temperature poly-silicon (LIPS) as an activelayer, the costs and defective ratio may be further lowered due tohigher mobility and other advantages of LIPS, and the performance of theTFT can be improved. In the conventional technology, however, exposureand development processes of at least 7-9 times are required during thepreparation of an LIPS-TFT in order to ensure good performance of N-typeand P-type LTPS-TFT to be prepared. In this case, the processes forpreparing the LTPS-TFT are increased, and so are the numbers of maskplates to be needed, which leads to complicated processes and highcosts.

SUMMARY

Embodiments of the present invention provide a poly-silicon TFT, apoly-silicon array substrate and a preparing method thereof, which havesimplified process and lower costs.

One embodiment of the present invention provides a method of preparing apoly-silicon TFT which comprises a doped region, the method comprisingthe following steps: forming a poly-silicon layer on a substrate,forming an active layer by a patterning process; forming a firstinsulating layer covering the active layer; forming, by a patterningprocess, via holes exposing the active layer in the first insulatinglayer at preset positions for forming a source electrode and a drainelectrode in subsequent steps; doping the active layer through the viaholes by a doping process to form a doped region; forming a source-drainmetal layer, and forming the source electrode and the drain electrode bya patterning process.

For example, the aforesaid method of preparing poly-silicon TFT mayfurther comprise: forming a gate metal layer, forming a gate electrodeby a patterning process; foaming a second insulating layer on thesubstrate where the gate electrode is formed.

In the method, for example, the poly-silicon TFT is an N-TFT, and thedoped region may be an N-type doped region.

In the method, for example, the doped elements may be one of P, As, andSb, or a mixture thereof.

In the method, for example, the poly-silicon TFT may be a P-TFT, and thedoped region may be a P-type doped region.

In the method, for example, the doped elements may be one of B, and In,or a mixture thereof.

Another embodiment of the present invention provides a poly-silicon TFTobtained by the aforesaid preparing method.

A further embodiment of the present invention provides a poly-siliconarray substrate, which comprises the aforesaid poly-silicon TFT.

A further embodiment of the present invention provides a method ofpreparing a poly-silicon array substrate which comprises an N-TFTincluding an N-type doped region and a P-TFT including a P-type dopedregion, the method comprising the following steps: forming apoly-silicon layer on a substrate, forming an active layer by apatterning process, doping the N-TFT or P-TFT active layer by a firstdoping process to form the N-type doped region or the P-type dopedregion; forming a first insulating layer covering the active layer;forming, by a patterning process, via holes in the first insulatinglayer at preset positions for forming source and drain electrodes of theN-TFT and source and drain electrodes of the P-TFT in subsequent steps;doping an exposed active layer region via the via holes by a seconddoping process, to form the P-type doped region or the N-type dopedregion, the element doping amount of the second doping process beingsmaller than that of the first doping process; forming a source-drainmetal layer, and forming the source electrode and the drain electrode bya patterning process.

For example, the preparing method may further comprise: forming a gatemetal layer, forming a gate electrode by a patterning process; forming asecond insulating layer on the substrate where the gate electrode isformed.

In the method, for example, the element doping amount of the seconddoping process may be ⅓˜⅔ of the element doping amount of the firstdoping process.

In the method, for example, the element doping amount of the seconddoping process may be ½ of the element doping amount of the first dopingprocess.

In the method, for example, the patterning process includes a half-tonemasking process, a grey-tone masking process, or a single-slit maskingprocess in the steps of forming the poly-silicon layer on the substrate,forming the active layer by the patterning process, doping the N-TFT orP-TFT active layer by the first doping process to form the N-type dopedregion or the P-type doped region.

For example, the aforesaid method may further comprise: forming a thirdinsulating layer, and forming, by a patterning process, via holes atpositions where the pixel electrode is connected to the drain electrodeof the TFT in the subsequent steps.

For example, the aforesaid method may further comprise: forming atransparent conductive layer, and forming a pixel electrode by apatterning process.

The method, for example, may further comprise forming a buffer layer onthe substrate prior to forming the poly-silicon layer.

In the method, for example, the doped elements in the N-type dopedregion of the N-TFT may be one of P, As, and Sb, or a mixture thereof.

In the method, for example, the doped elements in the P-type dopedregion of the P-TFT may be one of B, and In, or a mixture thereof.

A further embodiment of the present invention provides a poly-siliconarray substrate obtained by the aforesaid preparing method.

A further embodiment of the present invention provides a display device,which comprises the aforesaid poly-silicon array substrate.

The poly-silicon TFT, the poly-silicon array substrate and the preparingmethod thereof are provided in the embodiments of the present inventionby performing the doping process through via holes to form doped regionson both sides of the active layer and to form a corresponding TFT,thereby avoiding the requirement of dedicated mask plates for dopingprocess, reducing the numbers of mask plates used for preparing the TFTarray substrate, and lowering production costs.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to clearly illustrate the technical solution of the embodimentsof the invention, the drawings of the embodiments will be brieflydescribed in the following; it is obvious that the described drawingsare only related to some embodiments of the invention and thus are notlimitative of the invention.

FIG. 1 to FIG. 7 are cross-sectional schematic views of the poly-siliconTFT in each of the steps provided in an embodiment of the presentinvention;

FIG. 8 is a cross-sectional schematic view of another poly-silicon TFTprovided in an embodiment of the present invention; and

FIG. 9 to FIG. 18 are cross-sectional schematic views of thepoly-silicon array substrate in each of the steps provided in anembodiment of the present invention.

DETAILED DESCRIPTION

In order to make objects, technical details and advantages of theembodiments of the invention apparent, the technical solutions of theembodiments will be described in a clearly and fully understandable wayin connection with the drawings related to the embodiments of theinvention. Apparently, the described embodiments are just a part but notall of the embodiments of the invention. Based on the describedembodiments herein, those skilled in the art can obtain otherembodiment(s), without any inventive work, which should be within thescope of the invention.

Unless otherwise defined, the technical or scientific terms used hereinshall have the general meanings understandable for those ordinarilyskilled in the field of the present invention. The terms “first”,“second” . . . and the like in the description and in the claims, ifany, are used for distinguishing between similar elements and notnecessarily for describing any order, number or priority. The phrasessuch as “a”, “an,” “the” or similar shall not represent limitation ofnumbers, but mean existence of at least one. The phrases “include”,“comprise” or similar intend to mean the elements or objects before suchwords cover or are equivalent to the elements or objects listed aftersuch words, but other elements or objects are not exclusive. The phrases“joint”, “connect” or similar are not limited to physical or chemicalconnection, but also include electrical connection, no matter directlyor indirectly. The phrases “on”, “under”, “left”, “right” and etc. shallbe used only to represent relative positions, wherein, when the absoluteposition of the described object is changed, the relative positions maybe changed accordingly.

Embodiment 1

The present embodiment provides a method of preparing a poly-siliconTFT, which comprises the following steps.

S1. Forming a poly-silicon layer on the substrate, and forming an activelayer by a patterning process.

The patterning process is, for example, a photolithography patterningprocess, for example comprising: coating a photoresist layer on astructure layer to be patterned; exposing the photoresist layer using amask plate; developing the exposed photoresist layer to obtain aphotoresist pattern; etching the structure layer with the photoresistpattern, and optionally removing the photoresist pattern. The mask platefor example may be a single-tone or a dual-tone mask plate.

Prior to the preparation of the TFT array substrate, the substrate 1 maybe cleaned firstly to remove dusts from the substrate 1 so as to preventthe prepared TFT from deterioration of performance caused by the dusts.The substrate 1 may be a plastic substrate or a glass substrate, whereinthe glass substrate may be used for preparing a hard array substrate andthe plastic substrate may be used for preparing a soft array substrate.

After completion of the cleaning, a poly-silicon layer is formed on thesubstrate 1, either by directly forming the poly-silicon layer on thesubstrate or by firstly forming an amorphous silicon (a-Si) layer on thesubstrate and then crystallizing the a-Si layer. The method of directlyforming the poly-silicon layer or the a-Si layer may be chemical vapordeposition or the like. The method of crystallizing the a-Si layer mayinclude solid phase crystallization (SPC), laser crystallization ormetal induction crystallization (MIC) or the like.

After forming the poly-silicon layer, an active layer 2 is formed by apatterning process, which patterning process exemplarily includes thefollowing steps:

S101. Coating photoresist on the substrate formed with the poly-siliconlayer;

S102. Exposing and developing the substrate coated with the photoresistby a masking process so as to fiat in a photoresist pattern including aphotoresist-completely-retained region and aphotoresist-completely-removed region;

S103. Etching the poly-silicon layer in thephotoresist-completely-removed region by an etching process, so as toform the active layer 2 of the poly-silicon TFT; and

S104. Removing the remaining photoresist.

The schematic view of the formed structure is shown in FIG. 1.

S2. Forming a first insulating layer 3.

The first insulating layer 3 is formed on the substrate formed with theactive layer. The first insulating layer 3 may be prepared by such amethod as spin coating, chemical vapor deposition or the like. Theschematic view of the formed structure is shown in FIG. 2.

S3. Forming a gate metal layer and forming a gate electrode 4 by apatterning process.

For example, the gate metal layer is formed on the substrate formed withthe first insulating layer by a chemical vapor deposition or sputteringmethod.

The gate electrode 4 is formed by a patterning process, which patterningprocess exemplarily includes the following steps:

S301. Coating photoresist on the gate metal layer;

S302. Exposing and developing the substrate coated with the photoresistso as to form a photoresist pattern including aphotoresist-completely-retained region and aphotoresist-completely-removed region;

S303. Etching the gate metal layer of the photoresist-completely-removedregion by an etching process so as to form the gate electrode 4; and

S304. Removing the remaining photoresist.

The schematic view of the formed structure is shown in FIG. 3.

S4. Forming a second insulating layer 5.

The second insulating layer 5 is formed on the substrate subjected tothe step S3. The second insulating layer 5 may be prepared by such amethod as spin coating, chemical vapor deposition or the like. Theschematic view of the formed structure is shown in FIG. 4.

S5. Forming, by a patterning process, via holes at preset positions forforming source and drain electrodes in subsequent steps.

The via holes 6 is formed by a patterning process on the substratesubjected to the step S4, which patterning process exemplarily includesthe following steps:

S501. Coating photoresist on the substrate subjected to the step S4;

S502. Exposing and developing the substrate coated with the photoresistby a masking process so as to form a photoresist pattern including aphotoresist-completely-retained region and aphotoresist-completely-removed region;

S503. Etching the first insulating layer 3 and the second insulatinglayer 5 of the photoresist-completely-removed region by an etchingprocess, so as to form the via holes 6 penetrating through the firstinsulating layer 3 and the second insulating layer 5; and

S504. Removing the remaining photoresist.

The schematic view of the formed structure is shown in FIG. 5.

S6. Doping the active layer through the via holes by a doping process toform a doped region 201.

The doping process in the present step may be carried out by such amethod as ion implantation or the like. The structure formed afterdoping is shown in FIG. 6.

S7. Forming a source-drain metal layer, and forming a source electrodeand a drain electrode by a patterning process.

The source-drain metal layer is formed on the substrate subjected to thedoping process, for example, by such a method as sputtering or the like.Afterwards a patterning process is adopted to form the source electrodeand the drain electrode, which are connected to the doped regions of theactive layer through the via holes formed in the step S5. The patterningprocess exemplarily includes the following steps:

S701. Coating photoresist on the substrate formed with the source-drainmetal layer;

S702. Exposing and developing the substrate coated with the photoresistby a masking process so as to form a photoresist pattern including aphotoresist-completely-retained region and aphotoresist-completely-removed region;

S703. Etching the source-drain metal layer in thephotoresist-completely-removed region by an etching process, so as tofoini a source electrode 7 and a drain electrode 8.

The aforesaid poly-silicon TFT may be an N-TFT or a P-TFT. When it is anN-TFT, the doped region may be an N-type doped region, and the dopedelements may be one of P, As, and Sb, or a mixture thereof; when it is aP-TFT, the doped region may be a P-type doped region, and the dopedelements may be one of B, and In, or a mixture thereof.

S704. Removing the remaining photoresist.

The schematic view of the formed structure is shown in FIG. 7.

In the present embodiment, the source electrode and the drain electrodeof the TFT may also be prepared prior to the preparation of the gateelectrode and the second insulating layer. The preparing method is sameas that implemented in the aforesaid steps and is not dealt with herein.The formed structure is shown in FIG. 8.

In addition, the present embodiment further provides a poly-silicon TFTobtained by the aforesaid method of preparing the poly-silicon TFT. Thestructure of the poly-silicon TFT is shown in FIG. 7 or FIG. 8.

Corresponding to the poly-silicon TFT, the present embodiment furtherprovides a poly-silicon array substrate comprising the aforesaidpoly-silicon TFT. The poly-silicon array substrate may be applied tovarious display devices, for example, liquid crystal display device,organic light emitting diode (OLED) display device, e-paper displaydevice and so on.

The poly-silicon TFT and the preparing method thereof are provided inthe present embodiment by performing the doping process through viaholes to form doped regions on both sides of the active layer and toform a corresponding TFT, thereby avoiding the requirement of dedicatedmask plates for doping process, reducing the numbers of mask plates usedfor preparing the TFT array substrate, and lowering production costs.

Embodiment 2

Corresponding to the method of preparing a poly-silicon TFT, the presentembodiment further provides a method of preparing a poly-silicon arraysubstrate.

The array substrate in the embodiment of the present invention includesa plurality of gate lines and a plurality of data lines, which intersecteach other to define pixel units arranged in a matrix, each of the pixelunits comprising a thin film transistor as a switch element, and a pixelelectrode. For example, the gate electrode of the thin film transistorof each pixel unit is electrically connected to or integrally formedwith the corresponding gate line, the source electrode is electricallyconnected to or integrally formed with the corresponding data line, andthe drain electrode is electrically connected to or integrally formedwith the corresponding pixel electrode. The following description ismainly about one or more pixel units, but other pixel units may beformed similarly.

The poly-silicon array substrate of the present embodiment comprises anN-TFT including an N-type doped region and a P-TFT including a P-typedoped region. The pixel region (display region) 2 of the array substrateand the peripheral driving region 3 at the periphery of the pixel region2 may be respectively provided with an N-TFT and a P-TFT. The pixelregion 2 and the peripheral driving region 3 may be formed with thepoly-silicon TFTs of either the same type or the different types. In oneapplication, a P-TFT is formed in the peripheral driving region 3 whilean N-TFT is formed in the pixel region 2. The type and position of theTFT to be formed may be adjusted according to the practical needs andare not defined herein. The method of preparing the embodiment maycomprise the following steps.

A1. Forming a poly-silicon layer on a substrate, forming an active layerby a patterning process, and doping the N-TFT or P-TFT active layer by afirst doping process to form an N-type doped region or a P-type dopedregion.

The poly-silicon layer is formed on the substrate 1, either by directlyforming the poly-silicon layer on the substrate or by firstly forming anamorphous silicon (a-Si) layer on the substrate before crystallizing thea-Si layer. The method of directly forming the poly-silicon layer or thea-Si layer may be chemical vapor deposition or the like. The method ofcrystallizing the a-Si layer may include solid phase crystallization(SPC), laser crystallization or metal induction crystallization (MIC) orthe like.

The active layer is formed by a patterning process, which patterningprocess exemplarily includes the following steps:

A101. Coating photoresist on the substrate formed with the poly-siliconlayer;

A102. Exposing and developing the substrate coated with the photoresistby a masking process so as to form a photoresist pattern including aphotoresist-completely-retained region 403, aphotoresist-partially-retained region 402 and aphotoresist-completely-removed region 401; etching the poly-siliconlayer in the photoresist-completely-removed region 401 by an etchingprocess, so as to form the active layer 201 of the N-TFT and the activelayer 301 of the P-TFT, as shown in FIG. 9.

The masking process in the step A102 may be realized by using adual-tone mask plate, for example, a half-tone mask plate, a grey-tonemask plate, or a single-slit mask plate.

A103. Removing the photoresist of the partially-retained region 402,which may be realized by an ashing process. In the present step, thephotoresist-completely-retained region 403 may also be thinned andpartially retained.

A104. Doping, using a doping process, the exposed active layer after thephotoresist-partially-retained region 402 is removed in the step A103,so as to form a doped region 202.

The doping process may adopt such a method as ion implantation or thelike. If the N-type doped region is formed first, the doped elements inthis step may be one of P, As, and Sb, or a mixture thereof; if theP-type doped region is formed first, the doped elements in this step maybe one of B, and In, or a mixture thereof. The order of forming theP-type doped region and the N-type doped region does not affect themethod provided in the present embodiment, as long as the doped elementsare elements corresponding to the doped region. No more details aregiven here. The following steps are introduced by giving the example offorming the N-type doped region of N-TFT first. The formed structure isshown in FIG. 10.

A105. Removing the remaining photoresist to form an active layer 201 ofN-TFT having an N-type doped region 202 and an active layer 301 ofP-TFT.

The formed structure is shown in FIG. 11.

A2. Forming a first insulating layer.

The first insulating layer 5 is formed on the substrate formed with theactive layer. The first insulating layer 5 may be prepared by such amethod as spin coating, chemical vapor deposition or the like. Theschematic view of the formed structure is shown in FIG. 12.

A3. Forming a gate metal layer, and forming a gate electrode by apatterning process.

The gate metal layer is formed on the substrate formed with the firstinsulating layer 5 by a chemical vapor deposition or sputtering method.After the gate metal layer is formed, the gate electrode is formed by apatterning process, which patterning process exemplarily includes thefollowing steps:

A301. Coating photoresist on the substrate formed with the gate metallayer;

A302. Exposing and developing the substrate coated with the photoresistby a masking process so as to form a photoresist pattern including aphotoresist-completely-retained region and aphotoresist-completely-removed region;

A303. Etching the gate metal layer of the photoresist-completely-removedregion by an etching process so as to form the gate electrodes 203 and303.

The formed structure is shown in FIG. 13.

A4. Forming a second insulating layer.

The second insulating layer 6 is formed on the substrate formed with thegate electrodes. The second insulating layer 6 may be prepared by such amethod as spin coating or the like. The formed structure is shown inFIG. 14.

A5. Forming, by a patterning process, via holes at preset positions forforming source and drain electrodes of the N-TFT and source and drainelectrodes of the P-TFT in subsequent steps, the source and drainelectrodes of the N-TFT being connected through the via holes to theactive layer of the N-TFT, and the source and drain electrodes of theP-TFT being connected through the via holes to the active layer of theP-TFT;

The patterning process exemplarily includes the following steps:

A501. Coating photoresist on the substrate formed with the secondinsulating layer;

A502. Exposing and developing the substrate coated with the photoresistby a masking process so as to form a photoresist pattern including aphotoresist-completely-retained region and aphotoresist-completely-removed region;

A503. Etching the first insulating layer and the second insulating layerof the photoresist-completely-removed region by an etching process, soas to form via holes 204, 205, 304 and 305 at preset positions forforming the source and drain electrodes of the N-TFT and the source anddrain electrodes of the P-TFT in subsequent steps. The source and drainelectrodes of the N-TFT are connected through the via holes 204 and 205to the active layer of the N-TFT; the source and drain electrodes of theP-TFT are connected through the via holes 304 and 305 to the activelayer of the P-TFT.

A504. Removing the remaining photoresist.

The formed structure is shown in FIG. 15.

A6. Doping the active layer through the via holes by a second dopingprocess, to form the P-type doped region or the N-type doped region. Theformed structure is shown in FIG. 16.

The present step is introduced by giving the example of forming anN-type doped region in step A1 and forming a P-type doped region in thepresent step.

The second doping process may adopt such a method as ion implantation orthe like. By making use of the barrier effect of the first insulatinglayer 5, the second insulating layer 6 and the gate electrodes 203, 303,the active layer of the P-TFT is doped via the via holes 304, 305without using a mask plate, whereby the P-type doped region 302 isformed.

The doped elements in the P-type doped region 302 may be one of B, andIn, or a mixture thereof.

When the second doping process is performed, since the N-type dopedregion 202 of the N-TFT also comprises via holes 204 and 205, the P-typedoped elements may also enter the N-type doped region 202 through thevia holes 204 and 205 while doping. So, the doping amount of the P-typedoped element in the second doping process is smaller than the dopingamount of the N-type doped element in the first doping process. Thedoping amount may be controlled specifically by controlling theconditions (e.g. voltage, ion beam distribution and etc.) of the dopingprocess. In this case, although the P-type doped element may enter theN-type doped region 202 to be neutralized with the N-type doped elementin the N-type doped region 202, the doped region 202 still presentsN-type semiconductor properties because the doping amount of the P-typedoped element is smaller than that of the N-type doped element.

Preferably, the doping amount of the second doping process may be ⅓˜⅔ ofthe doping amount of the first doping process, and more preferably, thedoping amount of the second doping process may be ½ of the doping amountof the first doping process. Under the preferable conditions, both theprocess flow and the costs of mask plate can be saved, while the goodsemiconductor properties of the N-type doped region and the P-type dopedregion can be ensured.

A7. Forming a source-drain metal layer, and forming the source and drainelectrodes by a patterning process.

The source-drain metal layer is formed on the substrate subjected to thestep A6 by a sputtering method, chemical vapor deposition or the like.The source and drain electrodes are formed on the substrate formed withthe source-drain metal layer by a patterning process, which patterningprocess exemplarily includes the following steps:

A701. Coating photoresist on the substrate formed with the source-drainmetal layer;

A702. Exposing and developing the substrate coated with the photoresistby a masking process so as to form a photoresist pattern including aphotoresist-completely-retained region and aphotoresist-completely-removed region;

A703. Etching the source-drain metal layer in thephotoresist-completely-removed region by an etching process, so as toform source electrodes 206, 306 of the N-TFT and the P-TFT and drainelectrodes 207, 307 of the N-TFT and the P-TFT; and

A704. Removing the remaining photoresist.

The formed structure is shown in FIG. 17.

The method of preparing the poly-silicon array substrate provided in thepresent embodiment may prepare the source and drain electrodes of theN-TFT and the P-TFT before preparing the second insulating layer, andthen prepare the gate electrodes on the second insulating layer, whichcan achieve the same effect.

The method of preparing the array substrate may further comprise:

A8. Forming a transparent conductive layer, and forming a pixelelectrode by a patterning process.

The transparent conductive layer is formed on the substrate formed withthe source and drain electrodes by such a method as sputtering, chemicalvapor deposition, or the like. The material for the transparentconductive layer may be selected from ITO, IZO and etc., and preferablyan ITO material.

The pixel electrode is formed by a patterning process, which patterningprocess exemplarily includes the following steps.

A801. Coating photoresist on the substrate formed with the transparentconductive layer;

A802. Exposing and developing the substrate coated with the photoresistby a masking process so as to form a photoresist pattern including aphotoresist-completely-retained region and aphotoresist-completely-removed region;

A803. Etching the transparent conductive layer of thephotoresist-completely-removed region by an etching process, so as toform a pixel electrode; and

A804. Removing the photoresist of the completely-retained region.

The formed structure is shown in FIG. 18.

Prior to the preparation of the pixel electrode, an insulating layer maybe optionally prepared on the source and drain electrodes of the N-TFTand the P-TFT in order to protect the source and drain electrodes frombeing affected during the preparation of the pixel electrode. After thepreparation of the insulating layer, via holes may be formed on theinsulating layer, through which via holes the pixel electrode isconnected to the drain electrode of the P-TFT.

Preferably, prior to the preparation of the poly-silicon layer, themethod may further comprise:

A0. Forming a buffer layer on the substrate.

By preparing a buffer layer on the substrate, it can be avoided that theimpurities in the substrate enter the poly-silicon layer to affect theperformance of the TFT.

The present embodiment further provides a poly-silicon array substrateprepared by the aforesaid method.

The method of preparing the poly-silicon array substrate, thepoly-silicon array substrate, the display panel and the display deviceare provided in the embodiments by performing the doping process throughvia holes to form doped regions on both sides of the active layer and toform a corresponding TFT, thereby avoiding the requirement of dedicatedmask plates for doping process, reducing the numbers of mask plates usedfor preparing the TFT array substrate, and lowering production costs.

Corresponding to the poly-silicon array substrate, the embodimentfurther provides a display panel comprising said poly-silicon arraysubstrate.

Corresponding to the display panel, the embodiment further provides adisplay device comprising said display panel, for example, liquidcrystal display device, organic light emitting diode (OLED) displaydevice, e-paper display device and etc. The display device comprises anarray substrate according to any one of the aforesaid embodiments.

As for a liquid crystal display device, the array substrate and anopposed substrate are disposed opposite to each other so as to form aliquid crystal cell, and a liquid crystal material is filled in theliquid crystal cell. The opposed substrate is, for example, a colorfilter substrate. A pixel electrode in each pixel unit of the arraysubstrate acts to apply an electric field to controlling the rotationdegree of the liquid crystal material, so as to conduct a displayoperation. In another example, the liquid crystal display device furthercomprises a backlight source used to provide backlight for the arraysubstrate.

As for an OLED display device, a pixel electrode in each pixel unit ofthe array substrate functions as an anode or a cathode for driving anorganic light emitting material to emit light, so as to conduct displayoperation.

As for an e-paper display device, a pixel electrode in each pixel unitof the array substrate is used for driving the movement of e.g. thecharged particles in electronic ink so as to realize the display ofimages.

The above embodiments of the present invention are given by way ofillustration only and thus are not limitative of the protection scope ofthe present invention, which is determined by the attached claims.

1. A method of preparing a poly-silicon thin film transistor (TFT) whichcomprises a doped region, comprising the following steps: forming apoly-silicon layer on a substrate, and forming an active layer by apatterning process; forming a first insulating layer covering the activelayer; forming, by a patterning process, via holes exposing the activelayer in the first insulating layer at preset positions for forming asource electrode and a drain electrode in subsequent steps; doping theactive layer through the via holes by a doping process to form a dopedregion; and forming a source-drain metal layer, and forming the sourceelectrode and the drain electrode by a patterning process.
 2. The methodof preparing a poly-silicon TFT according to claim 1, furthercomprising: forming a gate metal layer, and forming a gate electrode bya patterning process; and forming a second insulating layer on thesubstrate formed with the gate electrode.
 3. The method of preparing apoly-silicon TFT according to claim 1, wherein the poly-silicon TFT isan N-TFT, and the doped region is an N-type doped region.
 4. The methodof preparing a poly-silicon TFT according to claim 3, wherein the dopedelements is one of P, As, and Sb, or a mixture thereof.
 5. The method ofpreparing a poly-silicon TFT according to claim 1, wherein thepoly-silicon TFT is a P-TFT, and the doped region is a P-type dopedregion.
 6. The method of preparing a poly-silicon TFT according to claim5, wherein the doped elements is one of B, and In, or a mixture thereof.7. A poly-silicon TFT obtained by the preparing method according toclaim
 1. 8. A poly-silicon array substrate, which comprises thepoly-silicon TFT according to claim
 7. 9. A method of preparing apoly-silicon array substrate which comprises an N-TFT including anN-type doped region and a P-TFT including a P-type doped region, themethod comprising the following steps: forming a poly-silicon layer on asubstrate, forming an active layer by a patterning process, and dopingthe N-TFT or P-TFT active layer by a first doping process to form theN-type doped region or the P-type doped region; forming a firstinsulating layer covering the active layer; forming, by a patterningprocess, via holes in the first insulating layer at preset positions forforming source and drain electrodes of the N-TFT and source and drainelectrodes of the P-TFT in subsequent steps; doping an exposed activelayer region via the via holes by a second doping process, to form theP-type doped region or the N-type doped region, the element dopingamount of the second doping process being smaller than that of the firstdoping process; and forming a source-drain metal layer, and forming thesource electrode and the drain electrode by a patterning process. 10.The method of preparing a poly-silicon array substrate according toclaim 9, further comprising: forming a gate metal layer, and forming agate electrode by a patterning process; and forming a second insulatinglayer on the substrate formed with the gate electrode.
 11. The method ofpreparing a poly-silicon array substrate according to claim 10, whereinthe element doping amount of the second doping process is ⅓˜⅔ of theelement doping amount of the first doping process.
 12. The method ofpreparing a poly-silicon array substrate according to claim 11, whereinthe element doping amount of the second doping process is ½ of theelement doping amount of the first doping process.
 13. The method ofpreparing a poly-silicon array substrate according to claim 10, whereinthe patterning process includes a half-tone masking process, a grey-tonemasking process, or a single-slit masking process in the steps offorming the poly-silicon layer on the substrate, forming the activelayer by the patterning process, doping the N-TFT or P-TFT active layerby the first doping process to form the N-type doped region or theP-type doped region.
 14. The method of preparing a poly-silicon arraysubstrate according to claim 10, further comprising: forming a thirdinsulating layer, and forming, by a patterning process, via holes atpositions where the pixel electrode is connected to the drain electrodeof the P-TFT in the subsequent steps.
 15. The method of preparing apoly-silicon array substrate according to claim 10, further comprising:forming a transparent conductive layer, and forming a pixel electrode bya patterning process.
 16. The method of preparing a poly-silicon arraysubstrate according to claim 10, further comprising: forming a bufferlayer on the substrate prior to forming the poly-silicon layer.
 17. Themethod of preparing a poly-silicon array substrate according to claim10, wherein the doped elements in the N-type doped region of the N-TFTis one of P, As, and Sb, or a mixture thereof.
 18. The method ofpreparing a poly-silicon array substrate according to claim 10, whereinthe doped elements in the P-type doped region of the P-TFT is one of B,and In or a mixture thereof.
 19. A poly-silicon array substrate obtainedby a preparing method according to claim
 9. 20. A display device,comprising a poly-silicon array substrate according to claim 19.